Hardware Implementation of Iterative Projection-Aggregation Decoding of Reed-Muller Codes
Abstract
In this work, we present a simplification and a corresponding hardware architecture for hard-decision recursive projection-aggregation (RPA) decoding of Reed-Muller (RM) codes. In particular, we transform the recursive structure of RPA decoding into a simpler and iterative structure with minimal error-correction degradation. Our simulation results for RM(7,3) show that the proposed simplification has a small error-correcting performance degradation (0.005 in terms of channel crossover probability) while reducing the average number of computations by up to 40%. In addition, we describe the first fully parallel hardware architecture for simplified RPA decoding. We present FPGA implementation results for an RM(6,3) code on a Xilinx Virtex-7 FPGA showing that our proposed architecture achieves a throughput of 171 Mbps at a frequency of 80 MHz.
Cite
@article{arxiv.2012.00581,
title = {Hardware Implementation of Iterative Projection-Aggregation Decoding of Reed-Muller Codes},
author = {Marzieh Hashemipour-Nazari and Kees Goossens and Alexios Balatsoukas-Stimming},
journal= {arXiv preprint arXiv:2012.00581},
year = {2020}
}