Related papers: A Clock Synchronizer for Repeaterless Low Swing On…
We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power…
Phase Frequency Detectors (PFDs) are essential components in Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) systems, responsible for comparing phase and frequency differences and generating up/down signals to regulate charge pumps…
We introduce PULSE, a sub-microsecond optical circuit-switched data centre network architecture controlled by distributed hardware schedulers. PULSE is a flat architecture that uses parallel passive coupler-based broadcast and select…
We present the first experimental confirmation of the so-called "self-phaselocked delay interferometry". This laser frequency stabilization technique consists basically in comparing the prompt laser signal with a delayed version of itself…
We introduce an interaction mechanism between oscillators leading to exact anti-phase and in-phase synchronization. This mechanism is applied to the coupling between two nonlinear oscillators with a limit cycle in phase space, leading to a…
In present paper, I propose a method for resolving the timing delays for output signals from an asynchronous sequential system. It will be used an example of an asynchronous sequential system that will set up an output signal when an input…
Space-based gravitational-wave detectors, such as LISA, record interferometric measurements on widely separated satellites. Their clocks are not synced actively. Instead, clock synchronization is performed in on-ground data processing. It…
In this paper, we propose a hybrid clock synchronization architecture for a cascaded sensor network based on GPS time service and synchronous frame protocol. The sensor's upper-level unit is called sensor management unit (SMU) which…
Clock synchronization and ranging over a wireless network with low communication overhead is a challenging goal with tremendous impact. In this paper, we study the use of time-to-digital converters in wireless sensors, which provides clock…
Interconnect properties position superconducting digital circuits to build large, high performance, power efficient digital systems. We report a board-to-board communication data link, which is a critical technological component that has…
We study the problem of clock synchronization in a networked system with arbitrary starts for all nodes. We consider a synchronous network of $n$ nodes, where each node has a local clock that is an integer counter. Eventually, clocks must…
Synchronization of two or more self-sustained oscillators is a well-known and studied phenomenon, appearing both in natural and designed systems. In some cases, the synchronized state is undesired, and the aim is to destroy synchrony by…
Phase locking experiments on vortex based spin transfer oscillators with an external microwave current are performed. We present clear evidence of phase locking, frequency pulling, as well as fractional synchronization in this system, with…
Time synchronization in any distributed network can be achieved by using application layer protocols for time correction. Time synchronization method proposed in this article uses symbol timing recovery at the physical layer to correct…
Experimental exploration of synchronization in scalable oscillator micro systems has unfolded a deeper understanding of networks, collective phenomena, and signal processing. Cavity optomechanical devices have played an important role in…
Time synchronization is a crucial requirement in quantum key distribution (QKD)8 protocols, ensuring accurate key generation via the correct assignment of bits of raw key and9 enabling eavesdropping detection via the precise recording of…
In this paper we report preliminary results of a simulation study on an energy-efficient time synchronization scheme based on source clock frequency recovery (SCFR) at sensor nodes in asymmetric wireless sensor networks (WSNs), where a head…
We demonstrate feedback and harmonic locking of chip-scale slot-type optomechanical oscillators to external low-noise reference clocks, with suppressed timing jitter by three orders of magnitude. The feedback and compensation techniques…
The task of implementing a supervisory controller is non-trivial, even though different theories exist that allow automatic synthesis of these controllers in the form of automata. One of the reasons for this discord is due to the…
Digital single-flux quantum (SFQ) technology promises to meet the demands of ultra low power and high speed computing needed for future exascale supercomputing platforms. However, clocking SFQ logic circuits remains a challenge due to the…