Related papers: A Clock Synchronizer for Repeaterless Low Swing On…
This paper proposes an algorithm for synthesis of clock-follow-data designs that provides robustness against timing violations for RSFQ circuits while maintaining high performance and minimizing area costs. Since superconducting logic gates…
Conventional circulators are made of magnetic ferrites and suffer from a cumbersome architecture, incompatibility with integrated circuit technology and inability for high frequency applications. To overcome these limitations, here we…
In principle, while coupled limit cycle oscillators can overcome mismatch in intrinsic rates and match their frequencies, but zero phase lag synchronization is just achievable in the limit of zero mismatch, i.e., with identical oscillators.…
Time synchronization is important for a variety of applications in wireless sensor networks including scheduling communication resources, coordinating sensor wake/sleep cycles, and aligning signals for distributed transmission/reception.…
This paper presents a new fast switching hybrid frequency synthesizer with wide locking range. The hybrid synthesizer is based on the tanlock loop with no delay block (NDTL) and is capable of integer as well as fractional frequency…
This letter proposes a new design of frequency-locked loop (FLL) which is based on synchronous (dq) reference frame instead of stationary ({\alpha}\b{eta}) reference frame. First, a synchronous reference frame FLL (briefly called SRF-FLL0)…
We present a power efficient clock-less fully asynchronous bit-serial Low Voltage Differential Signaling (LVDS) link with event-driven instant wake-up and self-sleep features, optimized for high speed inter-chip communication of…
The temporal behaviour of segmentation clock oscillations show phase synchrony via mean field like coupling of delta protein restricting to nearest neighbours only, in a configuration of cells arranged in a regular three dimensional array.…
In systems of coupled oscillators, the effects of complex signaling can be captured by time delays and phase shifts. Here, we show how time delays and phase shifts lead to different oscillator dynamics and how synchronization rates can be…
Supporting increasingly higher rates in wireless networks requires highly accurate clock synchronization across the nodes. Motivated by this need, in this work we consider distributed clock synchronization for half-duplex (HD) TDMA wireless…
A decision feedback circuit with integrated offset compensation is presented in this paper. The circuit is built around the sense amplifier comparator. The feedback loop is closed around the first stage of the comparator resulting in…
In this paper we study energy-efficient time synchronization schemes with focus on asymmetric wireless sensor networks, where a head node, which is connected to both wired & wireless networks, is equipped with a powerful processor and…
Consider an arbitrary network of communicating modules on a chip, each requiring a local signal telling it when to execute a computational step. There are three common solutions to generating such a local clock signal: (i) by deriving it…
We investigate and report an experimental confirmation of zero-lag synchronization (ZLS) in a system of three coupled time-delayed piecewise linear electronic circuits via dynamical relaying with different coupling configurations, namely…
This paper examines synchronization of computer clocks connected via a data network and proposes a skewless algorithm to synchronize them. Unlike existing solutions, which either estimate and compensate the frequency difference (skew) among…
Sharing a common clock signal among the nodes is crucial for communication in synchronized networks. This work presents a heartbeat-based synchronization scheme for body-worn nodes. The principles of this coordination technique combined…
To establish a time reference frame between two users in quantum key distribution, a synchronization calibration process is usually applied for the case of using gated mode single-photon detectors (SPDs). Traditionally, the synchronization…
A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks at 40 MHz, 80 MHz, or 640 MHz in the ALTIROC chip. The phase shifter has a coarse-phase shifter and a fine-phase shifter to achieve a step size of…
Clock generation is an essential part of wireless or wireline communication modules. To facilitate recent advancements in wireline-like communication and in-sensor computing modules at relatively lower data rates, ultra-low power, and…
Accurate network synchronization is a key enabler for services such as coherent transmission, cooperative decoding, and localization in distributed and cell-free networks. Unlike centralized networks, where synchronization is generally…