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Efficient low complexity error correcting code(ECC) is considered as an effective technique for mitigation of multi-bit upset (MBU) in the configuration memory(CM)of static random access memory (SRAM) based Field Programmable Gate Array…

Hardware Architecture · Computer Science 2018-10-24 Swagata Mandal , Sreetama Sarkar , Wong Ming Ming , Anupam Chattopadhyay , Amlan Chakrabarti

Reducing the threshold voltage of electronic devices increases their sensitivity to electromagnetic radiation dramatically, increasing the probability of changing the memory cells' content. Designers mitigate failures using techniques such…

Hardware Architecture · Computer Science 2023-07-14 David Freitas , David Mota , Clailton Lopes , Daniel Simões , Jarbas Silveira , João Mota , César Marcon

Voltage underscaling below the nominal level is an effective solution for improving energy efficiency in digital circuits, e.g., Field Programmable Gate Arrays (FPGAs). However, further undervolting below a safe voltage level and without…

Hardware Architecture · Computer Science 2019-04-01 Behzad Salami , Osman S. Unsal , Adrian Cristal Kestelman

The reliability of memory devices is affected by radiation induced soft errors. Multiple cell upsets (MCUs) caused by radiation corrupt data stored in multiple cells within memories. Error correction codes (ECCs) are typically used to…

Hardware Architecture · Computer Science 2023-08-01 Sayan Tripathi , Jhilam Jana , Jaydeb Bhaumik

Field Programmable Gate Arrays (FPGAs) are more prone to be affected by transient faults in presence of radiation and other environmental hazards compared to Application Specific Integrated Circuits (ASICs). Hence, error mitigation and…

Hardware Architecture · Computer Science 2015-09-24 Swagata Mandal , Rourab Paul , Suman Sau , Amlan Chakrabarti , Subhasis Chattopadhyay

Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and efficiency of an ASIC…

Hardware Architecture · Computer Science 2024-08-29 Julia Gonski , Aseem Gupta , Haoyi Jia , Hyunjoon Kim , Lorenzo Rota , Larry Ruckman , Angelo Dragone , Ryan Herbst

Spin Transfer Torque MRAMs are attractive due to their non-volatility, high density and zero leakage. However, STT-MRAMs suffer from poor reliability due to shared read and write paths. Additionally, conflicting requirements for data…

Other Computer Science · Computer Science 2016-06-20 Zoha Pajouhi , Xuanyao Fong , Anand Raghunathan , Kaushik Roy

Improvements in main memory storage density are primarily driven by process technology scaling, which negatively impacts reliability by exacerbating various circuit-level error mechanisms. To compensate for growing error rates, both memory…

Hardware Architecture · Computer Science 2022-04-25 Minesh Patel

Error Detection and Correction Codes (ECCs) are often used in digital designs to protect data integrity. Especially in safety-critical systems such as automotive electronics, ECCs are widely used and the verification of such complex logic…

Artificial Intelligence · Computer Science 2024-04-30 Aman Kumar

Electromagnetic fault injection (EMFI) is a well known technique used to disturb the behaviour of a chip for weakening its security. These attacks are mostly done on simple microcontrollers. On these targets, the fault effects are…

Cryptography and Security · Computer Science 2019-10-28 Thomas Trouchkine , Sébanjila Kevin Bukasa , Mathieu Escouteloup , Ronan Lashermes , Guillaume Bouffard

With the ever-growing storage density, high-speed, and low-cost data access, flash memory has inevitably become popular. Multi-level cell (MLC) NAND flash memory, which can well balance the data density and memory stability, has occupied…

Hardware Architecture · Computer Science 2018-02-14 Haochuan Song , Frankie Fu , Cloud Zeng , Jin Sha , Zaichen Zhang , Xiaohu You , Chuan Zhang

State-of-the-art techniques for addressing scaling-related main memory errors identify and repair bits that are at risk of error from within the memory controller. Unfortunately, modern main memory chips internally use on-die error…

Hardware Architecture · Computer Science 2021-12-21 Minesh Patel , Geraldo F. Oliveira , Onur Mutlu

Cryptographic algorithms are computationally costly and the challenge is more if we need to execute them in resource constrained embedded systems. Field Programmable Gate Arrays (FPGAs) having programmable logic de- vices and processing…

Hardware Architecture · Computer Science 2014-02-20 Sruti Agarwal , Sangeet Saha , Rourab Paul , Amlan Chakrabarti

Data transmission from superconducting electronic circuits, such as single flux quantum (SFQ) logic, to room-temperature electronics is susceptible to bit errors, which may result from flux trapping, fabrication defects, and process…

Signal Processing · Electrical Eng. & Systems 2026-02-13 Yerzhan Mustafa , Berker Peköz , Selçuk Köse

Computing-in-memory (CIM) promises to alleviate the Von Neumann bottleneck and accelerate data-intensive applications. Depending on the underlying technology and configuration, CIM enables implementing compute primitives in place, such as…

Hardware Architecture · Computer Science 2024-08-01 Preston Brazzle , Benjamin F. Morris , Evan McKinney , Peipei Zhou , Jingtong Hu , Asif Ali Khan , Alex K. Jones

Collective coherent (CC) errors are inevitable, as every physical qubit undergoes free evolution under its kinetic Hamiltonian. These errors can be more damaging than stochastic Pauli errors because they affect all qubits coherently,…

Quantum Physics · Physics 2025-11-14 En-Jui Chang

Inefficient data transfer between computation and memory inspired emerging processing-in-memory (PIM) technologies. Many PIM solutions enable storage and processing using memristors in a crossbar-array structure, with techniques such as…

Hardware Architecture · Computer Science 2021-05-11 Orian Leitersdorf , Ben Perach , Ronny Ronen , Shahar Kvatinsky

The size reduction of transistors in the latest flash memory generation has resulted in programming and data erasure issues within these designs. Consequently, ensuring reliable data storage has become a significant challenge for these…

Information Theory · Computer Science 2023-07-18 Saeideh Nabipour , Javad Javidan

Powerful Forward Error Correction (FEC) schemes are used in optical communications to achieve bit-error rates below $10^{-15}$. These FECs follow one of two approaches: concatenation of simpler hard-decision codes or usage of inherently…

Hardware Architecture · Computer Science 2017-09-01 Carlo Condo , Pascal Giard , François Leduc-Primeau , Gabi Sarkis , Warren J. Gross

Very deep submicron and nanometer technologies have increased notably integrated circuit (IC) sensitiveness to radiation. Soft errors are currently appearing into ICs working at earth surface. Hardened circuits are currently required in…

Hardware Architecture · Computer Science 2011-11-09 Celia Lopez-Ongil , Mario Garcia-Valderas , Marta Portela-Garcia , Luis Entrena-Arrontes
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