A 9.52 dB NCG FEC scheme and 164 bits/cycle low-complexity product decoder architecture
Abstract
Powerful Forward Error Correction (FEC) schemes are used in optical communications to achieve bit-error rates below . These FECs follow one of two approaches: concatenation of simpler hard-decision codes or usage of inherently powerful soft-decision codes. The first approach yields lower Net Coding Gains (NCGs), but can usually work at higher code rates and have lower complexity decoders. In this work, we propose a novel FEC scheme based on a product code and a post-processing technique. It can achieve an NCG of 9.52~dB at a BER of and 9.96~dB at a BER of , an error-correction performance that sits between that of current hard-decision and soft-decision FECs. A decoder architecture is designed, tested on FPGA and synthesized in 65 nm CMOS technology: its 164 bits/cycle worst-case information throughput can reach 100 Gb/s at the achieved frequency of 609~MHz. Its complexity is shown to be lower than that of hard-decision decoders in literature, and an order of magnitude lower than the estimated complexity of soft-decision decoders.
Cite
@article{arxiv.1610.06050,
title = {A 9.52 dB NCG FEC scheme and 164 bits/cycle low-complexity product decoder architecture},
author = {Carlo Condo and Pascal Giard and François Leduc-Primeau and Gabi Sarkis and Warren J. Gross},
journal= {arXiv preprint arXiv:1610.06050},
year = {2017}
}