Related papers: A planar Al-Si Schottky Barrier MOSFET operated at…
Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire…
This work presents a self-heating study of a 40-nm bulk-CMOS technology in the ambient temperature range from 300 K down to 4.2 K. A custom test chip was designed and fabricated for measuring both the temperature rise in the MOSFET channel…
We perform the characterization and modeling of a floating-gate device realized with a commercial 350-nm CMOS technology at cryogenic temperature. The programmability of the device offers a solution in the realization of a precise and…
Nickel silicide Schottky diodes formed on polycrystalline Si<P> films are proposed as temperature sensors of monolithic uncooled microbolometer IR focal plane arrays. Structure and composition of nickel silicide/polycrystalline silicon…
We investigate electronic transport properties of Schottky-barrier field-effect transistors (FET) based on double-walled carbon nanotubes (DWNT) with a semiconducting outer shell and a metallic inner one. These kind of DWNT-FET show…
We describe optical characterisation of a Strained Silicon Cold Electron Bolometer (CEB), operating on a $350~\mathrm{mK}$ stage, designed for absorption of millimetre-wave radiation. The silicon Cold Electron Bolometer utilises Schottky…
We show that carbon nanotube transistors operate as unconventional "Schottky barrier transistors", in which transistor action occurs primarily by varying the contact resistance rather than the channel conductance. Transistor characteristics…
A new method of refrigeration is proposed. Cooling is obtained by thermionic emission of electrons over periodic barriers in a multilayer geometry. These could be either Schottky barriers between metals and semiconductors or else barriers…
The cold source field-effect transistor (CSFET) is promising for reducing power dissipation in integrated circuits by engineering the density of states at the injecting source. Existing CSFET designs utilizing Dirac-source metals or…
Schottky barrier contact has been fabricated by thermal deposition of Al on (100) Ge (impurity concentration~1010/cm3 at 80K) that shows extrinsic p-type to intrinsic n-type transition near 180K. Both p and n-type Ge exhibits ideal Schottky…
Scalable, low-dissipation memory operating below 4 K is a critical requirement for superconducting and quantum computing systems. Existing cryogenic memory technologies rely on CMOS derivatives or hybrid architectures that incur leakage,…
Ambipolar currents in Germanium p-type nanowire Schottky barrier MOSFETs were calculated fully quantum-mechanically by using the multi-band k.p method and the non-equilibrium Green's function approach. We investigated the performance of…
State-of-the-art carbon nanotube field-effect transistors (CNFETs) behave as Schottky barrier (SB)-modulated transistors. It is known that vertical scaling of the gate oxide significantly improves the performance of these devices. However,…
This paper reports on the modulation of Schottky barrier heights (SBH) on three different orientations of $\beta$-Ga$_2$O$_3$ by insertion of an ultra-thin SiO$_2$ dielectric interlayer at the metal-semiconductor junction, which can…
We present first-principles calculations of Schottky barrier heights (SBHs) at interfaces relevant for silicon-based merged-element transmon qubit devices. Focusing on Al(111)/Si(111) and CoSi$_2$(111)/Si(111), we consider various possible…
Metal-semiconductor interfaces, known as Schottky junctions, have long been hindered by defects and impurities. Such imperfections dominate the electrical characteristics of the junction by pinning the metal Fermi energy. We report…
Large power consumption of silicon CMOS electronics is a challenge in very-large-scale integrated circuits and a major roadblock to fault-tolerant quantum computation. Matching the power dissipation of Si-MOSFETs to the thermal budget at…
Cryogenic CMOS technology (cryo-CMOS) offers a scalable solution for quantum device interface fabrication. Several previous works have studied the characterization of CMOS technology at cryogenic temperatures for various process nodes.…
Understanding of the electrical contact properties of semiconductor nanowire (NW) field effect transistors (FETs) plays a crucial role in employing semiconducting NWs as building blocks for future nanoelectronic devices and in the study of…
We demonstrate electrical injection and detection of spin-polarized electrons in silicon (Si) using epitaxially grown Fe_3Si/Si Schottky-tunnel-barrier contacts. By an insertion of a delta-doped n^+-Si layer (~ 10^19 cm^-3) near the…