Related papers: Clock Auto-synchronizing Method for BES III ETOF U…
A new fanning topology is proposed to precisely fan out fast control signals in the Beijing Spectrometer (BES III) end-cap time-of-flight (ETOF) electronics. However, uncertainty in transfer latency is introduced by the new fanning channel,…
The Beijing Spectrometer III (BESIII) endcap Time-Of-Filght (ETOF) was proposed to upgrade with Multigap Resistive Plate Chamber (MRPC) technology to substitute the current ETOF of scintillator+PMT for extending time resolutin better than…
The prototype of time digitizing system for the upgrade of BESIII endcap TOF (ETOF) is introduced in this paper. The ETOF readout electronics has a formation of distributed architecture that hit signal from multi-gap resistive plate chamber…
It is proposed to upgrade the endcap time-of-flight (ETOF) of the Beijing Spectrometer III (BESIII) with multi-gap resistive plate chamber (MRPC), aiming at overall time resolution about 80 ps. After the entire electronics system is ready,…
We present concept and implementation of a self-stabilizing Byzantine fault-tolerant distributed clock generation scheme for multi-synchronous GALS architectures in critical applications. It combines a variant of a recently introduced…
We revisit the approach to Byzantine fault-tolerant clock synchronization based on approximate agreement introduced by Lynch and Welch. Our contribution is threefold: (1) We provide a slightly refined variant of the algorithm yielding…
This paper presents the requirements and design of a Timing Synchronization System (TSS) for the Continuous Electron Beam Accelerator Facility (CEBAF) control system at Thomas Jefferson National Accelerator Facility. A clock module has been…
We give fault-tolerant algorithms for establishing synchrony in distributed systems in which each of the $n$ nodes has its own clock. Our algorithms operate in a very strong fault model: we require self-stabilisation, i.e., the initial…
Clock synchronization is a widely discussed topic in the engineering literature. Ensuring that individual clocks are closely aligned is important in network systems, since the correct timing of various events in a network is usually…
For tolerating Byzantine faults of both the terminal and communication components in self-stabilizing clock synchronization, the two-dimensional self-stabilizing Byzantine-fault-tolerant clock synchronization problem is investigated and…
We consider the clock synchronization problem in the (discrete) beeping model: Given a network of $n$ nodes with each node having a clock value $\delta(v) \in \{0,\ldots T-1\}$, the goal is to synchronize the clock values of all nodes such…
In extending fast digital clock synchronization to the bounded-delay model, the expected constant time Byzantine pulse resynchronization problem is investigated. In this problem, the synchronized state of the system should not only be…
A key distinguishing feature of single flux quantum (SFQ) circuits is that each logic gate is clocked. This feature forces the introduction of path-balancing flip-flops to ensure proper synchronization of inputs at each gate. This paper…
Consider an asynchronous network in a shared-memory environment consisting of n nodes. Assume that up to f of the nodes might be Byzantine (n > 12f), where the adversary is full-information and dynamic (sometimes called adaptive). In…
Electronic systems for qubit control and measurement serve as a bridge between quantum programming language and quantum information processors. With the rapid development of superconducting quantum circuit (SQC) technology, synchronization…
We present a novel FPGA-based bismuth germanate (BGO) time-of-flight (TOF) digitizer, implemented on an FPGA (VC707 evaluation kit, Xilinx). This digitizer was designed to address the recently highlighted characteristics of BGO, which…
We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC)…
Phase clocks are synchronization tools that implement a form of logical time in distributed systems. For systems tolerating transient faults by self-repair of damaged data, phase clocks can enable reasoning about the progress of distributed…
This paper addresses efficient hardware/software implementation approaches for the AES (Advanced Encryption Standard) algorithm and describes the design and performance testing algorithm for embedded system. Also, with the spread of…
An inexpensive and portable approach to measure the time an experimental event occurs as measured by a specific electronic clock is presented. The clock resets in active synchronization with the experimental AC-power cycle. This allows an…