Related papers: A 15 GSa/s, 1.5 GHz Bandwidth Waveform Digitizing …

A low-cost, stand-alone Global-Positioning-System-time-synchronized data acquisition system is described. The constructed prototype allows recoding up to four analog signals with a 16-bit resolution in variable ranges and a maximum sampling…

A simulation model is developed to train Artificial Neural Networks (ANN), for precise timing of PICOSEC Micromegas detector signals. The aim is to develop fast, online timing algorithms as well as minimising the information to be saved…

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope…

Aiming to measure the difference in arrival times of two coincident gamma-photons with an accuracy in the order of 200 ps, time-of-flight positron emission tomography systems commonly employ silicon photomultipliers (SiPMs) and…

Future detectors for high luminosity particle identification and ultra high energy neutrino observation would benefit from a digitizer capable of recording sensor elements with high analog bandwidth and large record depth, in a…

Reconfigurable photonic integrated circuits (PICs) can implement arbitrary operations and signal processing functionalities directly in the optical domain. Run-time configuration of these circuits requires an electronic control layer to…

This paper presents the design and characterisation of a front-end prototype ASIC for the ATLAS High Granularity Timing Detector, which is planned for the High-Luminosity phase of the LHC. This prototype, called ALTIROC1, consists of a…

This paper presents a differential 10-bit 2 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a precision-improvement technique. The proposed method breaks the direct tradeoff between the capacitive…

IEEE 802.11ad-based integrated sensing and communications (ISAC) have been identified as a potential solution for enabling next-generation intelligent transportation systems in the millimeter wave (mmW) spectrum. The radar functionality…

A new TDC chip has been developed for the COMPASS experiment at CERN. The resulting ASIC offers an unprecedented degree of flexibility and functionality. Its capability to handle highest hit and trigger input rates as well as its low power…

A highly integrated, high performance, and re-configurable device, which is designed for the Nitrogen-Vacancy center based quantum applications, is reported. The digital compartment of the device is fully implemented in a…

We propose a fast and near-optimal approach to joint channel-estimation, equalization, and decoding of coded single-carrier (SC) transmissions over frequency-selective channels with few-bit analog-to-digital converters (ADCs). Our approach…

Deep-learning accelerators are increasingly in demand; however, their performance is constrained by the size of the feature map, leading to high bandwidth requirements and large buffer sizes. We propose an adaptive scale feature map…

Integrated Sensing and Communication (ISAC) has attracted substantial attraction in recent years for spectral efficiency improvement, enabling hardware and spectrum sharing for simultaneous sensing and signaling operations. In-band Full…

We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream…

We present the prototype of a time-to-digital (TDC) ASIC for the upgrade of the ATLAS Monitored Drift Tube (MDT) detector for high-luminosity LHC operation. This ASIC is based on a previously submitted demonstrator ASIC designed for timing…

A sample rate converter(SRC) is designed to adjust the sampling rate of digital signals flexibly for different application requirements in the broadband signal processing system. In this paper, a novel parallel-serial structure is proposed…

Analog-to-digital conversion (ADC) is a key bottleneck in scaling DSP-centric receiver architectures to multiGigabit/s speeds. Recent information-theoretic results, obtained under ideal channel conditions (perfect synchronization, no…

To test and calibrate various detectors in nuclear and high energy physics experiments, a general purposed calibration instrument has been developed. All information including timing, amplitude and charge of signals can be directly obtained…

We have developed a new set of Application-Specific Integrated Circuits (ASICs) of the TARGET family (CTC and CT5TEA), designed for the readout of signals from photosensors in cameras of Imaging Atmospheric Cherenkov Telescopes (IACTs) for…