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In order to achieve fault tolerance, highly reliable system often require the ability to detect errors as soon as they occur and prevent the speared of erroneous information throughout the system. Thus, the need for codes capable of…

Information Theory · Computer Science 2010-02-08 Muzhir Al-Ani , Qeethara Al-Shayea

Crossbar resistive memory with the 1 Selector 1 Resistor (1S1R) structure is attractive for nonvolatile, high-density, and low-latency storage-class memory applications. As technology scales down to the single-nm regime, the increasing…

Systems and Control · Electrical Eng. & Systems 2021-04-30 Zehui Chen , Lara Dolecek

This paper summarizes our work on characterizing application memory error vulnerability to optimize datacenter cost via Heterogeneous-Reliability Memory (HRM), which was published in DSN 2014, and examines the work's significance and future…

Distributed, Parallel, and Cluster Computing · Computer Science 2018-05-11 Yixin Luo , Sriram Govindan , Bikash Sharma , Mark Santaniello , Justin Meza , Aman Kansal , Jie Liu , Badriddine Khessib , Kushagra Vaid , Onur Mutlu

Regenerating codes are efficient methods for distributed storage in storage networks, where node failures are common. They guarantee low cost data reconstruction and repair through accessing only a predefined number of arbitrarily chosen…

Information Theory · Computer Science 2017-11-09 Kaveh Mahdaviani , Ashish Khisti , Soheil Mohajer

Fault tolerance in Deep Neural Networks (DNNs) deployed on resource-constrained systems presents unique challenges for high-accuracy applications with strict timing requirements. Memory bit-flips can severely degrade DNN accuracy, while…

Efficient low complexity error correcting code(ECC) is considered as an effective technique for mitigation of multi-bit upset (MBU) in the configuration memory(CM)of static random access memory (SRAM) based Field Programmable Gate Array…

Hardware Architecture · Computer Science 2018-10-24 Swagata Mandal , Sreetama Sarkar , Wong Ming Ming , Anupam Chattopadhyay , Amlan Chakrabarti

NAND flash memory is ubiquitous in everyday life today because its capacity has continuously increased and cost has continuously decreased over decades. This positive growth is a result of two key trends: (1) effective process technology…

Hardware Architecture · Computer Science 2018-01-08 Yu Cai , Saugata Ghose , Erich F. Haratsch , Yixin Luo , Onur Mutlu

We consider a neural network (NN) that may experience memory faults and computational errors. In this paper, we propose a novel real-number-based error correction code (ECC) capable of detecting and correcting both memory errors and…

Neural and Evolutionary Computing · Computer Science 2026-02-03 Ziqing Li , Myung Cho , Qiutong Jin , Weiyu Xu

Chip Guard is a new approach to symbol-correcting error correction codes. It can be scaled to various data burst sizes and reliability levels. A specific version for DDR5 is described. It uses the usual DDR5 configuration of 8 data chips,…

Hardware Architecture · Computer Science 2023-01-19 Tanj Bennett

Compared to planar (i.e., two-dimensional) NAND flash memory, 3D NAND flash memory uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip. This allows 3D NAND flash memory to increase storage density…

Hardware Architecture · Computer Science 2018-11-13 Yixin Luo , Saugata Ghose , Yu Cai , Erich F. Haratsch , Onur Mutlu

On-chip memory (usually based on Static RAMs-SRAMs) are crucial components for various computing devices including heterogeneous devices, e.g., GPUs, FPGAs, ASICs to achieve high performance. Modern workloads such as Deep Neural Networks…

Hardware Architecture · Computer Science 2022-07-20 İsmail Emir Yüksel , Behzad Salami , Oğuz Ergin , Osman Sabri Ünsal , Adrian Cristal Kestelman

Non-volatile memory, such as resistive RAM (RRAM), is an emerging energy-efficient storage, especially for low-power machine learning models on the edge. It is reported, however, that the bit error rate of RRAMs can be up to 3.3% in the…

In this work, we study a recently proposed direct shaping code for flash memory. This rate-1 code is designed to reduce the wear for SLC (one bit per cell) flash by minimizing the average fraction of programmed cells when storing structured…

Information Theory · Computer Science 2020-07-14 Yi Liu , Paul H. Siegel

Resistive memories are considered a promising memory technology enabling high storage densities with in-memory computing capabilities. However, the readout reliability of resistive memories is impaired due to the inevitable existence of…

Information Theory · Computer Science 2019-04-22 Marwen Zorgui , Mohammed E. Fouda , Zhiying Wang , Ahmed M. Eltawil , Fadi Kurdahi

We propose binary discrete parametric channel models for multi-level cell (MLC) flash memories that provide accurate ECC performance estimation by modeling the empirically observed error characteristics under program/erase (P/E) cycling…

Information Theory · Computer Science 2016-11-17 Veeresh Taranalli , Hironori Uchikawa , Paul H. Siegel

We propose a lightweight scheme where the formation of a data block is changed in such a way that it can tolerate soft errors significantly better than the baseline. The key insight behind our work is that CNN weights are normalized between…

Machine Learning · Computer Science 2020-01-27 Masoomeh Jasemi , Shaahin Hessabi , Nader Bagherzadeh

Flash memory is a non-volatile computer memory comprised of blocks of cells, wherein each cell is implemented as either NAND or NOR floating gate. NAND flash is currently the most widely used type of flash memory. In a NAND flash memory,…

Information Theory · Computer Science 2009-11-23 Anxiao , Jiang , Robert Mateescu , Eitan Yaakobi , Jehoshua Bruck , Paul H. Siegel , Alexander Vardy , Jack K. Wolf

The progress in neuromorphic computing is fueled by the development of novel nonvolatile memories capable of storing analog information and implementing neural computation efficiently. However, like most other analog circuits, these devices…

Emerging Technologies · Computer Science 2021-07-12 Z. Fahimi , M. R. Mahmoodi , M. Klachko , H. Nili , H. Kim , D. B. Strukov

The last decade has witnessed the breakthrough of deep neural networks (DNNs) in many fields. With the increasing depth of DNNs, hundreds of millions of multiply-and-accumulate (MAC) operations need to be executed. To accelerate such…

Hardware Architecture · Computer Science 2022-11-29 Amro Eldebiky , Grace Li Zhang , Georg Boecherer , Bing Li , Ulf Schlichtmann

Modern DRAM modules are often equipped with hardware error correction capabilities, especially for DRAM deployed in large-scale data centers, as process technology scaling has increased the susceptibility of these devices to errors. To…

Hardware Architecture · Computer Science 2017-06-29 Yixin Luo , Saugata Ghose , Tianshi Li , Sriram Govindan , Bikash Sharma , Bryan Kelly , Amirali Boroumand , Onur Mutlu