Related papers: Design of a "Digital Atlas Vme Electronics" (DAVE)…
The energy consumption issue in distributed computing systems has become quite critical due to environmental concerns. In response to this, many energy-aware scheduling algorithms have been developed primarily by using the dynamic…
The current approach for new Advanced Driver Assistance System (ADAS) and Connected and Automated Driving (CAD) function development involves a significant amount of public road testing which is inefficient due to the number miles that need…
Designing field-programmable gate array (FPGA)-based accelerators for modern artificial intelligence workloads requires navigating a large and complex hardware design space encompassing architectural parameters, dataflow strategies, and…
The DArk Matter Particle Explorer (DAMPE) is a satellite-borne particle detector for measurements of high-energy cosmic rays and {\gamma}-rays. DAMPE has been operating smoothly in space for more than 8 years since launch on December 17,…
In this paper, we present a dynamically reconfigurable hardware accelerator called FADES (Fused Architecture for DEnse and Sparse matrices). The FADES design offers multiple configuration options that trade off parallelism and complexity…
Federated adversarial training can effectively complement adversarial robustness into the privacy-preserving federated learning systems. However, the high demand for memory capacity and computing power makes large-scale federated…
Transformers have shown superior performance on various vision tasks. Their large receptive field endows Transformer models with higher representation power than their CNN counterparts. Nevertheless, simply enlarging the receptive field…
The ATLAS detector at CERN's Large Hadron Collider will be exposed to proton-proton collisions from beams crossing at 40 MHz that have to be reduced to the few 100 Hz allowed by the storage systems. A three-level trigger system has been…
Complex electronic control unit (ECU) architectures, software models and in-vehicle networks are consistently improving safety and comfort functions in modern vehicles. However, the extended functionality and increased connectivity…
Deep Learning (DL) acceleration support in CPUs has recently gained a lot of traction, with several companies (Arm, Intel, IBM) announcing products with specialized matrix engines accessible via GEMM instructions. CPUs are pervasive and…
The Scientific Trigger Unit (UTS) is a satellite equipment designed to detect Gamma Ray Bursts (GRBs) observed by the onboard 6400 pixels camera ECLAIRs. It is foreseen to equip the low-Earth orbit French-Chinese satellite SVOM and acts as…
We developed a highly integrated and versatile electronic module to equip small nuclear physics experiments and lab teaching classes: the User friendly Configurable Trigger, scaler and delay Module for nuclear and particle physics (UCTM).…
Modern DAQ systems typically use the FPGA-based PCIe cards to concentrate and deliver the data to a computer used as an entry node of the data processing network. This paper presents a QEMU-based methodology for the co-development of the…
The LHC upgrade is planned to enhance the instantaneous luminosity during Run 3 from 2021 through 2023. The Phase-I upgrade of the trigger readout electronics for the ATLAS Liquid Argon (LAr) Calorimeters will be installed during the second…
We present a development of the ALFRED framework that includes support for the IPbus protocol, created for the Fast Interaction Trigger (FIT) detector in the ALICE experiment at CERN. This modification resolves the incompatibility between…
We propose dynamic resistive threshold-logic (DRTL) design based on non-volatile resistive memory. A threshold logic gate (TLG) performs summation of multiple inputs multiplied by a fixed set of weights and compares the sum with a…
In this paper, we design a PXI-based, multi-channel data-acquisition system (DAS) mainly applicable to recording one-shot fast transient pulses in nuclear physics experiments. The system consists of one NI PXIe-1085 chassis, containing a…
This article describes the ARM Scalable Vector Extension (SVE). Several goals guided the design of the architecture. First was the need to extend the vector processing capability associated with the ARM AArch64 execution state to better…
In this work, we propose FUSE, a novel GPU cache system that integrates spin-transfer torque magnetic random-access memory (STT-MRAM) into the on-chip L1D cache. FUSE can minimize the number of outgoing memory accesses over the…
Digital Signal Processing functions are widely used in real time high speed applications. Those functions are generally implemented either on ASICs with inflexibility, or on FPGAs with bottlenecks of relatively smaller utilization factor or…