Related papers: Process Optimization and Downscaling of a Single E…
For the past four decades, cost and features have driven CMOS scaling. Severe lithography and material limitations seen below the 20 nm node, however, are challenging the fundamental premise of affordable CMOS scaling. Just continuing to…
Dynamic reconfiguration of charge carriers in confined ion-channels under electrical stimulation produces memory effects, where the internal resistance depends on history of the electric field. Vermiculite nanofluidic devices harness this…
In this work, we study a recently proposed direct shaping code for flash memory. This rate-1 code is designed to reduce the wear for SLC (one bit per cell) flash by minimizing the average fraction of programmed cells when storing structured…
Solid-state nanopores, nm-sized holes in thin, freestanding membranes, are powerful single-molecule sensors capable of interrogating a wide range of target analytes, from small molecules to large polymers. Interestingly, due to their high…
The co-location of memory and processing is a core principle of neuromorphic computing. A local memory device for synaptic weight storage has long been recognized as an enabling element for large-scale, high-performance neuromorphic…
In this paper, we introduce a density-based topology optimization framework to design porous electrodes for maximum energy storage. We simulate the full cell with a model that incorporates electronic potential, ionic potential, and…
The memory hierarchy has a high impact on the performance and power consumption in the system. Moreover, current embedded systems, included in mobile devices, are specifically designed to run multimedia applications, which are memory…
In analog neuromorphic chips, designers can embed computing primitives in the intrinsic physical properties of devices and circuits, heavily reducing device count and energy consumption, and enabling high parallelism, because all devices…
We show storage of the circular polarisation of an optical field, transferring it to the spin-state of an individual electron confined in a single semiconductor quantum dot. The state is subsequently readout through the…
We numerically investigate the encoding and retrieval processes for a quantum memory realized in a semiconductor quantum dot, by focusing on the effect of inhomogeneously polarized nuclear spins whose polarization depends on the local…
The rapid development of artificial intelligence (AI), Internet of Things (IoT), and edge computing applications has posed severe challenges to conventional memory technologies in terms of density, speed, and energy consumption. Herein, a…
The semiconductor quantum dot nanopillar array in InAs/GaAs was fabricated. In consideration of the quantum dot density, the pillar diameter was determined as only a few quantum dots were involved in a pillar. The lattice constant of a…
Energy costs of information processing are growing exponentially. Bit erasure is a key problem in this energy-information nexus, and a number of seminal relationships have been deduced regarding the relationship between thermodynamic costs…
State-of-the-art models are now trained with billions of parameters, reaching hardware limits in terms of memory consumption. This has created a recent demand for memory-efficient optimizers. To this end, we investigate the limits and…
A superconducting loop stores persistent current without any ohmic loss, making it an ideal platform for energy efficient memories. Conventional superconducting memories use an architecture based on Josephson junctions (JJs) and have…
Implementing embedded neural network processing at the edge requires efficient hardware acceleration that couples high computational performance with low power consumption. Driven by the rapid evolution of network architectures and their…
Freeform nanostructures have the potential to support complex resonances and their interactions, which are crucial for achieving desired spectral responses. However, the design optimization of such structures is nontrivial and…
We apply evolutionary reinforcement learning to a simulation model in order to identify efficient time-dependent erasure protocols for a physical realization of a one-bit memory by an underdamped mechanical cantilever. We show that these…
We demonstrate wafer-scale integration of single electron memories based on carbon nanotube field effect transistors (cnfets) by a complete self assembly process. First, a dry self assembly based on a Hot Filament assisted Chemical Vapor…
We have performed a series of measurements on the low temperature behavior of a magnetic nano-particle system. Our results show striking memory effects in the dc magnetization. Dipolar interactions among the nano-particles {\em suppress}…