Related papers: Formal verification of a time-triggered hardware i…
Modern software systems are often realized by coordinating multiple heterogeneous parts, each responsible for specific tasks. These parts must work together seamlessly to satisfy the overall system requirements. To verify such complex…
The large number of recent JEDEC DRAM standard releases and their increasing feature set makes it difficult for designers to rapidly upgrade the memory controller IPs to each new standard. Especially the hardware verification is challenging…
This paper presents a hardware-in-the-loop (HIL) verification system for intelligent, camera-based in-body medical devices. A case study of a Video Capsule Endoscopy (VCE) prototype is used to illustrate the system's functionality. The…
Behavior-Interaction-Priority (BIP) is a layered embedded system design and verification framework that provides separation of functionality, synchronization, and priority concerns to simplify system design and to establish correctness by…
Modeling time related aspects is important in many applications of verification methods. For precise results, it is necessary to interpret time as a dense domain, e.g. using timed automata as a formalism, even though the system's resulting…
This study is aimed at showing applicability of mutual information, namely auto-mutual information function for condition monitoring in electrical motors, through age detection in accelerated motor aging. Vibration data collected in…
This paper presents a distributed hybrid algorithm that synchronizes the time and rate of a set of clocks connected over a network. Clock measurements of the nodes are given at aperiodic time instants and the controller at each node uses…
The rapid advancement of AI workloads and domain-specific architectures has led to increasingly diverse processor microarchitectures, whose design exploration requires fast and accurate performance validation. However, traditional workflows…
Frontier AI models pose increasing risks to public safety and international security, creating a pressing need for AI developers to provide credible guarantees about their development activities without compromising proprietary information.…
The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and…
We present an automated verification of the well-known modal logic cube in Isabelle/HOL, in which we prove the inclusion relations between the cube's logics using automated reasoning tools. Prior work addresses this problem but without…
This paper establishes a fundamental theory of secure clock synchronization. Accurate clock synchronization is the backbone of systems managing power distribution, financial transactions, telecommunication operations, database services,…
A driven linear oscillator and a feedback mechanism are two necessary elements of any classical periodic clock. Here, we introduce a novel, fully quantum clock using a driven oscillator in the quantum regime and coherent quantum feedback.…
We present Xenon, a solver-aided method for formally verifying that Verilog hardware executes in constant-time. Xenon scales to realistic hardware designs by drastically reducing the effort needed to localize the root cause of verification…
In this paper, we study the problem of robust global synchronization of resetting clocks in multi-agent networked systems, where by robust global synchronization we mean synchronization that is insensitive to arbitrarily small disturbances,…
Deadlock detection is a challenging issue in the analysis and design of on-chip networks. We have designed an algorithm to detect deadlocks automatically in on-chip networks with wormhole switching. The algorithm has been specified and…
We present an approach to unsolvability certification of temporal planning. Our approach is based on encoding the planning problem into a network of timed automata, and then using an efficient model checker on the network followed by a…
We propose a quantum analogue of the Huygens clock, in which the phases of two spins achieve synchronization through their interaction with a shared environment. The environment functions analogously to the escapement mechanism in a…
We present a simple and concise semantics for temporal planning. Our semantics are developed and formalised in the logic of the interactive theorem prover Isabelle/HOL. We derive from those semantics a validation algorithm for temporal…
Current formal verification of security protocols relies on specialized researchers and complex tools, inaccessible to protocol designers who informally evaluate their work with emulators. This paper addresses this gap by embedding symbolic…