Related papers: Formal verification of a time-triggered hardware i…

In the last decade, quantum computing has grown from novel physics experiments with a few qubits to commercial systems with hundreds of qubits. As quantum computers continue to grow in qubit count, the classical control systems must scale…

We present a method for the evaluation, at the first level of trigger, of logical conditions with high time resolution, using the digitized times of fast signals delivered in the detectors of high rate experiments. We describe a…

This paper presents a formalisation of pGCL in Isabelle/HOL. Using a shallow embedding, we demonstrate close integration with existing automation support. We demonstrate the facility with which the model can be extended to incorporate…

Different hardware platforms and their associated real time operating systems that can be used in an educational laboratory for illustrating engine electronic control unit hardware in the loop testing are presented and compared in this…

Hardware design faces a fundamental challenge: raising abstraction to improve productivity while maintaining control over low-level details like cycle accuracy. Traditional RTL design in languages like SystemVerilog composes modules through…

We consider the External Clock Synchronization problem in dynamic sensor networks. Initially, sensors obtain inaccurate estimations of an external time reference and subsequently collaborate in order to synchronize their internal clocks…

The sumcheck protocol, introduced in 1992, is an interactive proof which is a key component of many probabilistic proof systems in computational complexity theory and cryptography, some of which have been deployed. However, none of these…

Modern Integrated Circuits (ICs) are becoming increasingly complex, and so is their development process. Hardware design verification entails a methodical and disciplined approach to the planning, development, execution, and sign-off of…

High precision, synchronized clocks are essential to a growing number of Internet applications. Standard protocols and their associated server infrastructure have been shown to typically enable client clocks to synchronize on the order of…

We present concept and implementation of a self-stabilizing Byzantine fault-tolerant distributed clock generation scheme for multi-synchronous GALS architectures in critical applications. It combines a variant of a recently introduced…

Real-time systems rely on a distributed global time base. As any physical clock device suffers from noise, it is necessary to provide some kind of clock synchronization to establish such a global time base. Different clock synchronization…

The objective of this study is to detect and quantify the periodic behavior of the signals using topological methods. We propose to use delay-coordinate embeddings as a tool to measure the periodicity of signals. Moreover, we use persistent…

We demonstrate a two-qubit logic gate driven by near-field microwaves in a room-temperature microfabricated ion trap. We measure a gate fidelity of 99.7(1)\%, which is above the minimum threshold required for fault-tolerant quantum…

The CHERI architecture equips conventional RISC ISAs with significant architectural extensions that provide a hardware-enforced mechanism for memory protection and software compartmentalisation. Architectural capabilities replace…

In wireless sensor networks (WSNs), implementing a high-precision time synchronization scheme on resource-constrained sensor nodes is a major challenge. Our investigation of the practical implementation on a real testbed of the…

Mission-time Linear Temporal Logic (MLTL) is rapidly increasing in popularity as a specification logic, e.g., for runtime verification and model checking, driving a need for a trustworthy tool base for analyzing MLTL. In this work, we…

In the hardware design process, hardware components are usually described in a hardware description language. Most of the hardware description languages, such as Verilog and VHDL, do not have mathematical foundation and hence are not fit…

Formal verification of complex algorithms is challenging. Verifying their implementations goes beyond the state of the art of current automatic verification tools and usually involves intricate mathematical theorems. Certifying algorithms…

Security issues are playing dominant role in today's high speed communication systems. A fast and compact FPGA based implementation of the Data Encryption Standard (DES) and Triple DES algorithm is presented in this paper that is widely…

Objective: An electroencephalogram (EEG)-based brain-computer interface (BCI) enables direct communication between the human brain and a computer. Due to individual differences and non-stationarity of EEG signals, such BCIs usually require…