Related papers: Multiscale Metrology and Optimization of Ultra-Sca…

The design of a 1 micrometer gate length depletion-mode InSb quantum-well field-effect transistor (QWFET) with a 10 nm-thick Al2O3 gate dielectric has been optimized using a quantum corrected self-consistent Schrodinger-Poisson (QCSP) and…

In this work, quantum ballistic simulation study of a III-V tri-gate MOSFET has been presented. At the same time, effects of device parameter variation on ballistic, subthrshold and short channel performance is observed and presented. The…

After more than 30 years of validation of Moore's law, the CMOS technology has already entered the nanoscale (sub-100nm) regime and faces strong limitations. The nanowire transistor is one candidate which has the potential to overcome the…

We study the evolution of the quantum scattering time by gate voltage training in the topological insulator based on InAs/GaSb/InAs trilayer quantum wells. Depending on the minimal gate voltage applied during a gate voltage sweep cycle, the…

GaSb/InAs heterojunction tunnel field-effect transistors are strong candidates in building future low-power integrated circuits, as they could provide both steep subthreshold swing and large ON-state current ($I_{\rm{ON}}$). However, at…

We propose an effective method to optimize the working parameters (WPs) of microwave-driven quantum logical gates implemented with multi-level physical qubits. We show that by treating transitions between each pair of levels independently,…

A multiscale simulation method is developed to model a quantum dot (QD) array of germanium (Ge) holes for quantum computing. Guided by three-dimensional numerical quantum device simulations of QD structures, an analytical model of the…

Quantum computation and quantum simulation require a versatile gate set to optimize circuit compilation for practical applications. However, existing platforms are often limited to specific gate types or rely on parametric couplers to…

Quantization in the inversion layer and phase coherent transport are anticipated to have significant impact on device performance in 'ballistic' nanoscale transistors. While the role of some quantum effects have been analyzed qualitatively…

Gate-layouts of spin qubit devices are commonly adapted from previous successful devices. As qubit numbers and the device complexity increase, modelling new device layouts and optimizing for yield and performance becomes necessary.…

Quantum state tomography (QST) represents an essential tool for the characterization, verification, and validation (QCVV) of quantum processors. Only for a few idealized scenarios, there are analytic results for the optimal measurement set…

Quantum machine learning offers promising advantages for classification tasks, but noise, decoherence, and connectivity constraints in current devices continue to limit the efficient execution of feature map-based circuits. Gate Assessment…

The utility of near-term quantum computers and simulators is likely to rely upon software-hardware co-design, with error-aware algorithms and protocols optimized for the platforms they are run on. Here, we show how knowledge of noise in a…

A key requirement to perform simulations of large quantum systems on near-term quantum hardware is the design of quantum algorithms with short circuit depth that finish within the available coherence time. A way to stay within the limits of…

The effective use of current Noisy Intermediate-Scale Quantum (NISQ) devices is often limited by the noise which is caused by interaction with the environment and affects the fidelity of quantum gates. In transmon qubit systems, the quantum…

The silicon nanowire transistor (SNWT) is a promising device structure for future integrated circuits, and simulations will be important for understanding its device physics and assessing its ultimate performance limits. In this work, we…

The cross-over from quasi-two- to quasi-one-dimensional electron transport subject to transverse electric fields and perpendicular magnetic fields are studied in the diffusive to quasiballistic and zero-field to quantum Hall regime.…

Gate-tunable high-mobility InSb/In_{1-x}Al_{x}Sb quantum wells (QWs) grown on GaAs substrates are reported. The QW two-dimensional electron gas (2DEG) channel mobility in excess of 200,000 cm^{2}/Vs is measured at T=1.8K. In asymmetrically…

We investigated Capacitance-Voltage (C-V) characteristics of the Depletion Mode Buried Channel InGaAs/InAs Quantum Well FET by using Self-Consistent method incorporating Quantum Mechanical (QM) effects. Though the experimental results of…

State-of-the-art superconducting quantum processors containing tens to hundreds of qubits have demonstrated the building blocks for realizing fault-tolerant quantum computation. Nonetheless, a fundamental barrier to scaling further is the…