Related papers: Level Shifter Design for Low Power Applications

This paper introduces a voltage multiplier (VM) circuit which can step up a minimum voltage of 150 mV (peak). The operation and characteristics of this converter circuit are described. The voltage multiplier circuit is also tested with…

Phasor measurement units (PMUs) provide a high-resolution view of the power system at the locations where they are placed. As such, it is desirable to place them in bulk in low voltage distribution circuits. However, the power consumption…

Multilevel inverters are used to improve powerquality and reduce component stresses. This paper describesand compares two multilevel cascaded three phase inverterimplementations with two different modulation techniques: PhaseShifted Pulse…

This paper presents an output capacitor-less low-dropout regulator (LDO) with a bias switching scheme for biomedical applications with dual-range load currents. Power optimization is crucial for systems with multiple activation modes such…

Throughout the world, the numbers of researchers or hardware designer struggle for the reducing of power dissipation in low power VLSI systems. This paper presented an idea of using the power gating structure for reducing the sub threshold…

This paper presents SleepViT, a custom accelerator ASIC for real-time, low-power sleep stage classification in wearable devices. At the core of SleepViT is a lightweight vision transformer model specifically optimized for…

This paper proposes and evaluates a novel architecture for a low-power Time-to-Digital Converter with high resolution, optimized for both integration in multichannel chips and high rate operation (40 Mconversion/s/channel). This converter…

Steep transistors are crucial in lowering power consumption of the integrated circuits. However, the difficulties in achieving steepness beyond the Boltzmann limit experimentally have hindered the fundamental challenges in application of…

The ubiquitous use of sensing and signal processing is increasing exponentially with the advance of the Internet of Everything (IoE). In this context, the design of every time more power efficient sensor nodes is a must. Within these nodes,…

As the Internet-of-Things (IoT) applications become more and more pervasive, IoT end nodes are requiring more and more computational power within a few mW of power envelope, coupled with high-speed and energy-efficient inter-chip…

A robust power gating design using Graphene Nano-Ribbon Field Effect Transistors (GNRFET) is proposed using 16nm technology. The Power Gating (PG) structure is composed of GNRFET as a power switch and MOS power gated module. The proposed…

A low-cost reconfiguration stage connected at the output of balanced three-phase, multi-terminal ac/dc/ac converters can increase the feasible set of power injections substantially, increasing converter utilization and therefore achieving a…

The subthreshold leakage current in transistors has become a critical limiting factor for realizing ultra-low-power transistors. The leakage current is predominantly dictated by the long thermal tail of the charge carriers. We propose a…

This paper presents a fully-integrated CMOS voltage reference designed in a 90 nm process node using low voltage threshold (LVT) transistor models. The voltage reference leverages subthreshold operation and near-weak inversion…

This paper proposes a novel switching algorithm for modular multilevel converters (MMCs) that significantly reduces the switching frequency while fulfilling all control objectives required for their proper operation. Unlike in the…

This paper addresses a novel five-transistor (5T) CMOS SRAM design with high performance and reliability in 65nm CMOS, and illustrates how it reduces the dynamic power consumption in comparison with the conventional and low-power 6T SRAM…

The main promise of tunnel FETs (TFETs) is to enable supply voltage ($V_{DD}$) scaling in conjunction with dimension scaling of transistors to reduce power consumption. However, reducing $V_{DD}$ and channel length ($L_{ch}$) typically…

Nanopositioning techniques currently applied to characterize physical properties of materials interesting for applications at the microscopic scale rely on high-voltage electronic control circuits that should have the lowest possible noise…

A four-stage operational transconductance amplifier (OTA) for ultra-low-power applications is introduced in this paper. The proposed circuit inclusive of frequency compensation requires minimal transistor count and passives, overcoming the…

This paper presents a low power, low jitter LC phase locked loop (PLL) which has been designed and fabricated in a commercial 0.25-um Silicon-on-Sapphire CMOS technology. Random jitter and deterministic jitter of the PLL are 1.3 ps and 7.5…