Related papers: Fast trigger logic with digitized time information
We propose an algorithm, deployable on a highly-parallelized graph computing architecture, to perform rapid reconstruction of charged-particle trajectories in the high energy collisions at the Large Hadron Collider and future colliders. We…
With the high bunch-crossing and interaction rates and potentially large event sizes the experiments at the LHC challenge data acquisition and trigger systems. Within the ATLAS experiment, a multi-level trigger system based on hardware and…
Modern high-energy physics experiments collect data using dedicated complex multi-level trigger systems which perform an online selection of potentially interesting events. In general, this selection suffers from inefficiencies. A further…
A scheme to implement quantum logic gates by manipulating trapped ions through interaction with monochromatic external laser field and quantized cavity field, beyond the Lamb-Dicke regime, is presented. Characteristic times, for…
This paper introduces the problem of learning to place logic blocks in Field-Programmable Gate Arrays (FPGAs) and a learning-based method. In contrast to previous search-based placement algorithms, we instead employ Reinforcement Learning…
Field Programmable Gate Array (FPGA) is widely used in acceleration of deep learning applications because of its reconfigurability, flexibility, and fast time-to-market. However, conventional FPGA suffers from the tradeoff between chip area…
This paper addresses a critical preliminary step in radar signal processing: detecting the presence of a radar signal and robustly estimating its bandwidth. Existing methods which are largely statistical feature-based approaches face…
Several compelling beyond the Standard Model scenarios predict signals that result in unconventional charged particle trajectories. Signatures for which unusual tracks are the most conspicuous feature pose significant challenges for…
We characterized the front-end electronics used to process high-frequency signals from low-gain avalanche diodes (LGADs) at the Fermilab Test Beam Facility. LGADs are silicon detectors employed for charged particle tracking, offering…
Time-triggered and event-triggered control strategies for stabilization of an unstable plant over a rate-limited communication channel subject to unknown, bounded delay are studied and compared. Event triggering carries implicit…
The online reconstruction of muon tracks in High Energy Physics experiments is a highly demanding task, typically performed with programmable logic boards, such as FPGAs. Complex analytical algorithms are executed in a quasi-real-time…
Analog multiplexing appears to be a promising solution for modern transmitters, where speed is the primary limitation. The objective is the development of a low-cost solution to compare different digital to analog (DAC) schemes. In…
Fully Field Programmable Gate Array (FPGA)based digitizer for high-resolution time and energy measurement is an attractive low cost solution for the readout electronics in positron emission computed tomography (PET)detector. In recent…
Given a discrete-state continuous-time reactive system, like a digital circuit, the classical approach is to first model it as a state transition system and then prove its properties. Our contribution advocates a different approach: to…
This paper presents a novel statistical state-dependent timing model for voltage over scaled (VoS) logic circuits that accurately and rapidly finds the timing distribution of output bits. Using this model erroneous VoS circuits can be…
The use of spatio-temporal logics in control is motivated by the need to impose complex spatial and temporal behavior on dynamical systems, and to control these systems accordingly. Synthesizing correct-by-design control laws is a…
Digital correlators play a significant role in dynamic light scattering (DLS) technology, which characterizes particle size distribution. We present a field programmable gate array (FPGA)-based digital correlator that can be applied to…
The CMS experiment has been designed with a two-level trigger system: the Level 1 (L1) Trigger, implemented on custom-designed electronics, and the High Level Trigger (HLT), a streamlined version of the CMS reconstruction and analysis…
We propose dynamic resistive threshold-logic (DRTL) design based on non-volatile resistive memory. A threshold logic gate (TLG) performs summation of multiple inputs multiplied by a fixed set of weights and compares the sum with a…
Novel electronic devices can often be operated in a plethora of ways, which makes testing circuits comprised of them difficult. Often, no single tool can simultaneously analyze the operating margins, maximum speed, and failure modes of a…