FPGA Divide-and-Conquer Placement using Deep Reinforcement Learning
Hardware Architecture
2024-04-23 v1 Artificial Intelligence
Machine Learning
Abstract
This paper introduces the problem of learning to place logic blocks in Field-Programmable Gate Arrays (FPGAs) and a learning-based method. In contrast to previous search-based placement algorithms, we instead employ Reinforcement Learning (RL) with the goal of minimizing wirelength. In addition to our preliminary learning results, we also evaluated a novel decomposition to address the nature of large search space when placing many blocks on a chipboard. Empirical experiments evaluate the effectiveness of the learning and decomposition paradigms on FPGA placement tasks.
Cite
@article{arxiv.2404.13061,
title = {FPGA Divide-and-Conquer Placement using Deep Reinforcement Learning},
author = {Shang Wang and Deepak Ranganatha Sastry Mamillapalli and Tianpei Yang and Matthew E. Taylor},
journal= {arXiv preprint arXiv:2404.13061},
year = {2024}
}
Comments
accepted by ISEDA2024