English

Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm

Hardware Architecture 2024-01-12 v1

Abstract

One of the key challenges when operating microcontrollers in harsh environments such as space is radiation-induced Single Event Upsets (SEUs), which can lead to errors in computation. Common countermeasures rely on proprietary radiation-hardened technologies, low density technologies, or extensive replication, leading to high costs and low performance and efficiency. To combat this, we present Trikarenos, a fault-tolerant 32-bit RISC-V microcontroller SoC in an advanced TSMC 28nm technology. Trikarenos alleviates the replication cost by employing a configurable triple-core lockstep configuration, allowing three Ibex cores to execute applications reliably, operating on ECC-protected memory. If reliability is not needed for a given application, the cores can operate independently in parallel for higher performance and efficiency. Trikarenos consumes 15.7mW at 250MHz executing a fault-tolerant matrix-matrix multiplication, a 21.5x efficiency gain over state-of-the-art, and performance is increased by 2.96x when reliability is not needed for processing, with a 2.36x increase in energy efficiency.

Keywords

Cite

@article{arxiv.2310.02045,
  title  = {Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm},
  author = {Michael Rogenmoser and Luca Benini},
  journal= {arXiv preprint arXiv:2310.02045},
  year   = {2024}
}

Comments

4 pages, 4 figures, accepted by IEEE International Conference on Electronics Circuits and Systems (ICECS) 2023