Digital Computing-in-Memory (DCIM) is an innovative technology that integrates multiply-accumulation (MAC) logic directly into memory arrays to enhance the performance of modern AI computing. However, the need for customized memory cells and logic components currently necessitates significant manual effort in DCIM design. Existing tools for facilitating DCIM macro designs struggle to optimize subcircuit synthesis to meet user-defined performance criteria, thereby limiting the potential system-level acceleration that DCIM can offer. To address these challenges and enable agile design of DCIM macros with optimal architectures, we present SynDCIM, a performance-aware DCIM compiler that employs multi-spec-oriented subcircuit synthesis. SynDCIM features an automated performance-to-layout generation process that aligns with user-defined performance expectations. This is supported by a scalable subcircuit library and a multi-spec-oriented searching algorithm for effective subcircuit synthesis. The effectiveness of SynDCIM is demonstrated through extensive experiments and validated with a test chip fabricated in a 40nm CMOS process. Testing results reveal that designs generated by SynDCIM exhibit competitive performance when compared to state-of-the-art manually designed DCIM macros.
@article{arxiv.2411.16806,
title = {SynDCIM: A Performance-Aware Digital Computing-in-Memory Compiler with Multi-Spec-Oriented Subcircuit Synthesis},
author = {Kunming Shao and Fengshi Tian and Xiaomeng Wang and Jiakun Zheng and Jia Chen and Jingyu He and Hui Wu and Jinbo Chen and Xihao Guan and Yi Deng and Fengbin Tu and Jie Yang and Mohamad Sawan and Tim Kwang-Ting Cheng and Chi-Ying Tsui},
journal= {arXiv preprint arXiv:2411.16806},
year = {2025}
}
Comments
Accepted by 2025 Design, Automation & Test in Europe Conference & Exhibition (DATE) as a regular paper