This work presents the design of an RS(31,27) Reed Solomon encoder for a 3.2 Gbps serial transmitter in 0.18 um CMOS technology. The proposed encoder is designed with a novel full parallel structure optimized for high speed and high stability. One data frame contains 2 interleaved RS(31,27) codes and thus it can correct at most 20 bits of consecutive errors. A corresponding decoder is implemented on Xilinx Kintex-7 FPGA.
@article{arxiv.1806.02173,
title = {Study of Full Parallel RS(31,27) Encoder for a 3.2 Gbps Serial Transmitter in 0.18 um CMOS Technology},
author = {Guangyu Zhang and Quan Sun and Tiankuan Liu and Datao Gong and Dongxu Yang and Yi Feng and Jian Wang},
journal= {arXiv preprint arXiv:1806.02173},
year = {2019}
}