Simulating spin systems on IANUS, an FPGA-based computer
Disordered Systems and Neural Networks
2009-11-13 v1 Hardware Architecture
Abstract
We describe the hardwired implementation of algorithms for Monte Carlo simulations of a large class of spin models. We have implemented these algorithms as VHDL codes and we have mapped them onto a dedicated processor based on a large FPGA device. The measured performance on one such processor is comparable to O(100) carefully programmed high-end PCs: it turns out to be even better for some selected spin models. We describe here codes that we are currently executing on the IANUS massively parallel FPGA-based system.
Keywords
Cite
@article{arxiv.0704.3573,
title = {Simulating spin systems on IANUS, an FPGA-based computer},
author = {F. Belletti and M. Cotallo and A. Cruz and L. A. Fernández and A. Gordillo and A. Maiorano and F. Mantovani and E. Marinari and V. Martín-Mayor and A. Muñoz-Sudupe and D. Navarro and S. Pérez-Gaviro and J. J. Ruiz-Lorenzo and S. F. Schifano and D. Sciretti and A. Tarancón and R. Tripiccione and J. L. Velasco},
journal= {arXiv preprint arXiv:0704.3573},
year = {2009}
}