This paper describes JANUS, a modular massively parallel and reconfigurable FPGA-based computing system. Each JANUS module has a computational core and a host. The computational core is a 4x4 array of FPGA-based processing elements with nearest-neighbor data links. Processors are also directly connected to an I/O node attached to the JANUS host, a conventional PC. JANUS is tailored for, but not limited to, the requirements of a class of hard scientific applications characterized by regular code structure, unconventional data manipulation instructions and not too large data-base size. We discuss the architecture of this configurable machine, and focus on its use on Monte Carlo simulations of statistical mechanics. On this class of application JANUS achieves impressive performances: in some cases one JANUS processing element outperfoms high-end PCs by a factor ~ 1000. We also discuss the role of JANUS on other classes of scientific applications.
@article{arxiv.0710.3535,
title = {JANUS: an FPGA-based System for High Performance Scientific Computing},
author = {F. Belletti and M. Cotallo and A. Cruz and L. A. Fernández and A. Gordillo and M. Guidetti and A. Maiorano and F. Mantovani and E. Marinari and V. Martín-Mayor and A. Muñoz-Sudupe and D. Navarro and G. Parisi and S. Pérez-Gaviro and M. Rossi and J. J. Ruiz-Lorenzo and S. F. Schifano and D. Sciretti and A. Tarancón and R. Tripiccione and J. L. Velasco},
journal= {arXiv preprint arXiv:0710.3535},
year = {2017}
}
Comments
11 pages, 6 figures. Improved version, largely rewritten, submitted to Computing in Science & Engineering