Serially Concatenated IRA Codes
Abstract
We address the error floor problem of low-density parity check (LDPC) codes on the binary-input additive white Gaussian noise (AWGN) channel, by constructing a serially concatenated code consisting of two systematic irregular repeat accumulate (IRA) component codes connected by an interleaver. The interleaver is designed to prevent stopping-set error events in one of the IRA codes from propagating into stopping set events of the other code. Simulations with two 128-bit rate 0.707 IRA component codes show that the proposed architecture achieves a much lower error floor at higher SNRs, compared to a 16384-bit rate 1/2 IRA code, but incurs an SNR penalty of about 2 dB at low to medium SNRs. Experiments indicate that the SNR penalty can be reduced at larger blocklengths.
Keywords
Cite
@article{arxiv.0709.4466,
title = {Serially Concatenated IRA Codes},
author = {Taikun Cheng and Krishnamoorthy Sivakumar and Benjamin J. Belzer},
journal= {arXiv preprint arXiv:0709.4466},
year = {2007}
}
Comments
Forty-Fifth Annual Allerton Conference on Communication, Control, and Computing, 2007, 4 pages, 4 figures