Related papers: Serially Concatenated IRA Codes
Algorithms are presented that efficiently shape the parity bits of systematic irregular repeat-accumulate (IRA) low-density parity-check (LDPC) codes by following the sequential encoding order of the accumulator. Simulations over additive…
This paper addresses the prediction of error floors of low-density parity-check (LDPC) codes with variable nodes of constant degree in the additive white Gaussian noise (AWGN) channel. Specifically, we focus on the performance of the…
We propose a technique to design finite-length irregular low-density parity-check (LDPC) codes over the binary-input additive white Gaussian noise (AWGN) channel with good performance in both the waterfall and the error floor region. The…
Structured codes based on lattices were shown to provide enlarged capacity for multi-user communication networks. In this paper, we study capacity-approaching irregular repeat accumulate (IRA) codes over integer rings $\mathbb{Z}_{2^{m}}$…
In this paper we construct low-density parity-check (LDPC) codes from transversal designs with low error-floors over the additive white Gaussian noise (AWGN) channel. The constructed codes are based on transversal designs that arise from…
In this paper, we presented three approaches to improve the design of Kite codes (newly proposed rateless codes), resulting in an ensemble of rate-compatible LDPC codes with code rates varying "continuously" from 0.1 to 0.9 for additive…
We present a new class of irregular low-density parity-check (LDPC) codes for moderate block lengths (up to a few thousand bits) that are well-suited for rate-compatible puncturing. The proposed codes show good performance under puncturing…
In this paper, we propose an efficient method to reduce error floors in quantum error correction using non-binary low-density parity-check (LDPC) codes. We identify and classify cycle structures in the parity-check matrix where estimated…
The design of low-density parity-check (LDPC) code ensembles optimized for a finite number of decoder iterations is investigated. Our approach employs EXIT chart analysis and differential evolution to design such ensembles for the binary…
The protograph low-density parity-check (LDPC) codes possess many attractive properties, such as the low encoding/decoding complexity and better error floor performance, and hence have been successfully applied to different types of…
We propose a new low-density parity-check code construction scheme based on 2-lifts. The proposed codes have an advantage of admitting efficient hardware implementations. With the motivation of designing codes with low error floors, we…
Cyclic liftings are proposed to lower the error floor of low-density parity-check (LDPC) codes. The liftings are designed to eliminate dominant trapping sets of the base code by removing the short cycles which form the trapping sets. We…
This paper considers the problem of code design for a channel where communications and radar systems coexist, modeled as having both Additive White Gaussian Noise (AWGN) and Additive Radar Interference (ARI). The issue of how to adapt or…
Protograph low-density-parity-check (LDPC) are considered to design near-capacity low-rate codes over the binary erasure channel (BEC) and binary additive white Gaussian noise (BIAWGN) channel. For protographs with degree-one variable nodes…
We discuss error floor asympotics and present a method for improving the performance of low-density parity check (LDPC) codes in the high SNR (error floor) region. The method is based on Tanner graph covers that do not have trapping sets…
This short paper explores density evolution (DE) for low-density parity-check (LDPC) codes at signal-to-noise-ratios (SNRs) that are significantly above the decoding threshold. The focus is on the additive white Gaussian noise channel and…
Most multi-dimensional (more than two dimensions) lattice partitions only form additive quotient groups and lack multiplication operations. This prevents us from constructing lattice codes based on multi-dimensional lattice partitions…
Irregular repeat-accumulate Root-Check LDPC codes based on Progressive Edge Growth (PEG) techniques for block-fading channels are proposed. The proposed Root-Check LDPC codes are {both suitable for channels under $F = 2, 3$ independent…
Spinal codes is a new family of capacity-achieving rateless codes that has been shown to achieve better rate performance compared to Raptor codes, Strider codes, and rateless Low-Density Parity-Check (LDPC) codes. This correspondence…
This paper presents several new construction techniques for low-density parity-check (LDPC) and systematic repeat-accumulate (RA) codes. Based on specific classes of combinatorial designs, the improved code design focuses on high-rate…