Nowadays nanoscale combinational circuits are facing significant reliability challenges including soft errors and process variations. This paper presents novel process variation-aware placement strategies that include two algorithms to increase the reliability of combinational circuits against both Single Event Transients (SETs) and Multiple Event Transients (METs). The first proposed algorithm is a global placement method (called SeaPlace-G) that places the cells for hardening the circuit against SETs by solving a quadratic formulation. Afterwards, a detailed placement algorithm (named SeaPlace-D) is proposed to increase the circuit reliability against METs by solving a linear programming optimization problem. Experimental results show that SeaPlace-G and SeaPlace-D averagely achieve 41.78% and 32.04% soft error reliability improvement against SET and MET, respectively. Moreover, when SeaPlace-D is followed by SeaPlace-G, MET reduction can be improved by up to 53.3%.
@article{arxiv.2112.04136,
title = {SeaPlace: Process Variation Aware Placement for Reliable Combinational Circuits against SETs and METs},
author = {Kiarash Saremi and Hossein Pedram and Behnam Ghavami and Mohsen Raji and Zhenman Fang and Lesley Shannon},
journal= {arXiv preprint arXiv:2112.04136},
year = {2021}
}