In this paper, the SHIP4LLRF (Scalable Hardware Integrated Platform for LLRF) based on 6U VPX-standard was designed preliminarily, which includes 6U mother board and two HPC FPGA mezzanine cards (FMCs). The ADC and DAC FMC is based on ADS54J60 from TI and LTC2000Y-16 form ADI, respectively. The system mother board is based on Xilinx Kintex UltraScale KU060, which also features 64-bit DDR4 SDRAM, QSFP and USB3.0 interfaces. Each FMC connector is assigned 58 pairs of LVDS standard IOs and 8 pairs of GTH high-speed serial lanes. Besides, the mother board is equipped with the self-developed ZYNQBee2 module based on ZYNQ7010 for slow control such as EPICS. All ADC or DAC raw data in each SHIP4LLEF is compressed loss-less without triggering and transmitted to the process board. A scalar quantization method which is in development is used for lossless compression of ADC raw data, the process board will decompress the ADC data and perform a digital algorithm to measure the amplitude and phase of the high frequency signal. This de-sign is scalable for testing and upgradability, mean-while, the trigger-less data transmission enable this system participate in both local (rack-scale) and accelerator-wide communication networks.
@article{arxiv.2311.03841,
title = {Preliminary Design of Scalable Hardware Integrated Platform for LLRF Application},
author = {Lin Jiang and Jingjun Wen and Tao Xue and Xiaowei Guo and Haoyan Yang and Qiutong Pan and Jianmin Li and Yinong Liu and Liangjun Wei},
journal= {arXiv preprint arXiv:2311.03841},
year = {2023}
}
Comments
Talk presented at LLRF Workshop 2023 (LLRF2023, arXiv: 2310.03199)