Power Scaling in High Speed Analog-to-Digital Converters using Photonic Time Stretch Technique
Abstract
Factors that contribute to the rapid increase in power dissipation as a function of input bandwidth in high speed electronic Analog-to-Digital Converters (ADCs) are discussed. We find that the figure of merit (FOM), defined as the energy required per conversion step, increases linearly with bandwidth for high-speed ADCs with moderate to high resolution, or equivalently, the power dissipation increases quadratically. It is shown that by use of photonic time-stretch technique, it is possible to have ADCs in which this FOM remains constant for up to 10 GHz input RF frequency. Using this technique, it is also possible to overcome the barrier to achieving high resolution caused by clock jitter and speed limitations of electronics in such ADCs. Use of optics is actively being pursued for reducing power dissipation and achieving higher data-rates for board-level and chip-level serial communication links. In the same manner, we expect that optics will also help in reducing power dissipation in high-speed ADCs in addition to providing broader bandwidths.
Keywords
Cite
@article{arxiv.0901.2767,
title = {Power Scaling in High Speed Analog-to-Digital Converters using Photonic Time Stretch Technique},
author = {Shalabh Gupta and George C. Valley and Robert H. Walden and Bahram Jalali},
journal= {arXiv preprint arXiv:0901.2767},
year = {2009}
}
Comments
Submitted to Optics Express on December 08, 2008