Performance Comparison of Quasi-Delay-Insensitive Asynchronous Adders
Hardware Architecture
2019-07-26 v1
Abstract
In this technical note, we provide a comparison of the design metrics of various quasi-delay-insensitive (QDI) asynchronous adders, where the adders correspond to diverse architectures. QDI adders are robust, and the objective of this technical note is to point to those QDI adders which are suitable for low power/energy and less area. This information could be valuable for a resource-constrained low power VLSI design scenario. Non-QDI adders are excluded from the comparison since they are not robust although they may have optimized design metrics. All the QDI adders were realized using a 32/28nm CMOS process.
Keywords
Cite
@article{arxiv.1907.10826,
title = {Performance Comparison of Quasi-Delay-Insensitive Asynchronous Adders},
author = {P Balasubramanian},
journal= {arXiv preprint arXiv:1907.10826},
year = {2019}
}
Comments
arXiv admin note: substantial text overlap with arXiv:1903.09433