Temporal computing promises to mitigate the stringent area constraints and clock distribution overheads of traditional superconducting digital computing. To design a scalable, area- and power-efficient superconducting network on chip (NoC), we propose packet-switched superconducting temporal NoC (PaST-NoC). PaST-NoC operates its control path in the temporal domain using race logic (RL), combined with bufferless deflection flow control to minimize area. Packets encode their destination using RL and carry a collection of data pulses that the receiver can interpret as pulse trains, RL, serialized binary, or other formats. We demonstrate how to scale up PaST-NoC to arbitrary topologies based on 2x2 routers and 4x4 butterflies as building blocks. As we show, if data pulses are interpreted using RL, PaST-NoC outperforms state-of-the-art superconducting binary NoCs in throughput per area by as much as 5x for long packets.
@article{arxiv.2210.09484,
title = {PaST-NoC: A Packet-Switched Superconducting Temporal NoC},
author = {Darren Lyles and Patricia Gonzalez-Guerrero and Meriam Gay Bautista and George Michelogiannakis},
journal= {arXiv preprint arXiv:2210.09484},
year = {2023}
}
Comments
14 pages, 18 figures, 2 tables. In press in IEEE Transactions on Applied Superconductivity