Partial Sums Generation Architecture for Successive Cancellation Decoding of Polar Codes
Hardware Architecture
2015-01-12 v1
Abstract
Polar codes are a new family of error correction codes for which efficient hardware architectures have to be defined for the encoder and the decoder. Polar codes are decoded using the successive cancellation decoding algorithm that includes partial sums computations. We take advantage of the recursive structure of polar codes to introduce an efficient partial sums computation unit that can also implements the encoder. The proposed architecture is synthesized for several codelengths in 65nm ASIC technology. The area of the resulting design is reduced up to 26% and the maximum working frequency is improved by ~25%.
Cite
@article{arxiv.1309.7818,
title = {Partial Sums Generation Architecture for Successive Cancellation Decoding of Polar Codes},
author = {Guillaume Berhault and Camille Leroux and Christophe Jego and Dominique Dallet},
journal= {arXiv preprint arXiv:1309.7818},
year = {2015}
}
Comments
Submitted to IEEE Workshop on Signal Processing Systems (SiPS)(26 April 2012). Accepted (28 June 2013)