Machine learning is playing an increasingly significant role in emerging mobile application domains such as AR/VR, ADAS, etc. Accordingly, hardware architects have designed customized hardware for machine learning algorithms, especially neural networks, to improve compute efficiency. However, machine learning is typically just one processing stage in complex end-to-end applications, involving multiple components in a mobile Systems-on-a-chip (SoC). Focusing only on ML accelerators loses bigger optimization opportunity at the system (SoC) level. This paper argues that hardware architects should expand the optimization scope to the entire SoC. We demonstrate one particular case-study in the domain of continuous computer vision where camera sensor, image signal processor (ISP), memory, and NN accelerator are synergistically co-designed to achieve optimal system-level efficiency.
@article{arxiv.1801.06274,
title = {Mobile Machine Learning Hardware at ARM: A Systems-on-Chip (SoC) Perspective},
author = {Yuhao Zhu and Matthew Mattina and Paul Whatmough},
journal= {arXiv preprint arXiv:1801.06274},
year = {2018}
}