This work demonstrates that porous helical WOx architectures enable a distinct low-power regime for planar ITO/WOx/ITO resistive random-access devices. While thin film and helical devices behave similarly at a 5 mA compliance, only helical devices sustain reproducible operation at 500 uA, where RESET voltages reduce by ~60%, switching currents decrease by 68-75%, and SET/RESET power drops by ~89% and ~83%. With helical devices operating at 500 uA, the memory window expands 400-600% due to selective suppression of high-resistive-state leakage, yielding both lower-power and improved read margin in a regime inaccessible to thin film devices. These results highlight geometry-driven field enhancement and confinement as practical design principles for low-power, high-margin resistive memories and point toward opportunities in transparent, flexible, and high-surface-area material systems.
@article{arxiv.2510.17831,
title = {Impact of Switching Layer Architecture on Power Consumption in RRAM},
author = {John F. Hardy and Jack A. Garrard and Guilherme S. Y. Giardini and Carlo R. daCunha},
journal= {arXiv preprint arXiv:2510.17831},
year = {2025}
}