2.5D integration is an important technique to tackle the growing cost of manufacturing chips in advanced technology nodes. This poses the challenge of providing high-performance inter-chiplet interconnects (ICIs). As the number of chiplets grows to tens or hundreds, it becomes infeasible to hand-optimize their arrangement in a way that maximizes the ICI performance. In this paper, we propose HexaMesh, an arrangement of chiplets that outperforms a grid arrangement both in theory (network diameter reduced by 42%; bisection bandwidth improved by 130%) and in practice (latency reduced by 19%; throughput improved by 34%). MexaMesh enables large-scale chiplet designs with high-performance ICIs.
@article{arxiv.2211.13989,
title = {HexaMesh: Scaling to Hundreds of Chiplets with an Optimized Chiplet Arrangement},
author = {Patrick Iff and Maciej Besta and Matheus Cavalcante and Tim Fischer and Luca Benini and Torsten Hoefler},
journal= {arXiv preprint arXiv:2211.13989},
year = {2023}
}