FPGA Design and Implementation of Fixed-Point Fast Divider Using Goldschmidt Division Algorithm and Mitchell Multiplication Algorithm

This paper presents a variable bit-width fixed-point fast divider using Goldschmidt division algorithm and Mitchell multiplication algorithm. Described using Verilog HDL and implemented on a Xilinx XC7Z020-2CLG400I FPGA, the proposed divider achieves over 99% computational accuracy with a minimum latency of 99.1 ns, which is 31.7 ns faster than existing single-precision dividers. Compared with a Goldschmidt divider using a Vedic multiplier, the proposed design reduces Slice Registers by 46.68%, Slice LUTs by 4.93%, and Slices by 11.85%, with less than 1% accuracy loss and only 24.1 ns additional delay. These results demonstrate an improved balance between computational speed and resource utilization, making the divider well-suited for high-performance FPGA-based systems with strict resource constraints.