Disguising Topology and Side-Channel Information through Covert Gate- and ML-Enabled IP Camouflaging
Abstract
Semiconductor intellectual property (IP) theft incurs hundreds of billions in annual losses, driven by advanced reverse engineering (RE) techniques. Traditional ``cryptic'' IC camouflaging methods typically focus on hiding localized gate functionality but remain vulnerable to system-level structural analysis. This paper explores ``mimetic deception,'' where a functional IP (F) is designed to structurally and visually masquerade as a completely different appearance IP (A). We provide a comprehensive evaluation of three deceptive methodologies: IP Camouflage, Graph Matching, and DNAS-NAND Gate Array, analyzing their resilience against GNN-based node classification, and Differential Power Analysis (DPA). Crucially, we demonstrate that mimetic deception achieves a novel anti-side-channel defense: by forcing the mis-classification of cryptographic primitives, the adversary is led to apply an incorrect power model, causing the DPA attack to fail. Our results validate that this multi-layered approach effectively thwarts the entire RE toolchain by poisoning the structural and logical data used for netlist understanding.
Keywords
Cite
@article{arxiv.2603.25904,
title = {Disguising Topology and Side-Channel Information through Covert Gate- and ML-Enabled IP Camouflaging},
author = {Junling Fan and David Koblah and Domenic Forte},
journal= {arXiv preprint arXiv:2603.25904},
year = {2026}
}