This paper suggests a practical "hybrid" synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at the circuit level. We show how to optimize stage-resolution to minimize the power in a pipelined ADC. Exploration (via detailed synthesis) of several ADC configurations is used to show that a 4-3-2... resolution distribution uses the least power for a 13-bit 40 MSPS converter in a 0.25 μm CMOS process.
Cite
@article{arxiv.0710.4722,
title = {Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters},
author = {Yu-Tsun Chien and Dong Chen and Jea-Hong Lou and Gin-Kou Ma and Rob A. Rutenbar and Tamal Mukherjee},
journal= {arXiv preprint arXiv:0710.4722},
year = {2011}
}
Comments
Submitted on behalf of EDAA (http://www.edaa.com/)