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Delay Monitor Circuit for Sensitive Nodes in SRAM-Based FPGA

Space Physics 2018-07-31 v1 Hardware Architecture Instrumentation and Detectors

Abstract

This paper presents a novel monitor circuit architecture and experiments performed for detection of extra combinational delays in a high frequency SRAM-Based FPGA on delay sensitive nodes due to transient ionizing radiation.

Keywords

Cite

@article{arxiv.1807.11311,
  title  = {Delay Monitor Circuit for Sensitive Nodes in SRAM-Based FPGA},
  author = {Mostafa Darvishi and Yves Audet and Yves Blaquiere},
  journal= {arXiv preprint arXiv:1807.11311},
  year   = {2018}
}

Comments

6 Figures, 5 pages, 1 table