Auto-Generation of Pipelined Hardware Designs for Polar Encoder

Zhiwei Zhong; Xiaohu You; Chuan Zhang

Auto-Generation of Pipelined Hardware Designs for Polar Encoder

Hardware Architecture 2018-01-03 v1

Authors: Zhiwei Zhong , Xiaohu You , Chuan Zhang

Abstract

This paper presents a general framework for auto-generation of pipelined polar encoder architectures. The proposed framework could be well represented by a general formula. Given arbitrary code length $N$ and the level of parallelism $M$ , the formula could specify the corresponding hardware architecture. We have written a compiler which could read the formula and then automatically generate its register-transfer level (RTL) description suitable for FPGA or ASIC implementation. With this hardware generation system, one could explore the design space and make a trade-off between cost and performance. Our experimental results have demonstrated the efficiency of this auto-generator for polar encoder architectures.

Keywords

polar encoder pipelined architecture auto-generation hardware design register-transfer level FPGA ASIC

Cite

@article{arxiv.1801.00472,
  title  = {Auto-Generation of Pipelined Hardware Designs for Polar Encoder},
  author = {Zhiwei Zhong and Xiaohu You and Chuan Zhang},
  journal= {arXiv preprint arXiv:1801.00472},
  year   = {2018}
}

Auto-Generation of Pipelined Hardware Designs for Polar Encoder

Abstract

Keywords

Cite

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