The planned high-luminosity upgrade of the Large Hadron Collider (LHC) at CERN will bring much higher data rates that are far above the capabilities of currently installed software-based data processing systems. Therefore, new methods must be used to facilitate on-the-fly extraction of scientifically significant information from the immense flow of data produced by LHC particle detectors. This paper focuses on implementation of a tau lepton triggering algorithm in FPGA. Due to the algorithm's complexity and strict technical requirements, its implementation in FPGA fabric becomes a particularly challenging task. The paper presents a study of algorithm development with the help of High-Level Synthesis (HLS) technique that can generate hardware description from C++ code. Various architectural solutions and optimizations that were tried out during the design architecture exploration process are also discussed in the paper.
@article{arxiv.2410.20430,
title = {Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis},
author = {Sergei Devadze and Christine Elizabeth Nielsen and Dmitri Mihhailov and Peeter Ellervee},
journal= {arXiv preprint arXiv:2410.20430},
year = {2024}
}
Comments
7 pages, 6 figures, 2024 IEEE Nordic Circuits and Systems Conference (NORCAS)