The main target of this article is to propose for the first time a physics-based continuous and symmetric compact model that accurately captures IV experimental dependencies induced by geometrical scaling effects for graphene transistor (GFET) technologies. Such a scalable model is an indispensable ingredient for the boost of large-scale GFET applications, as it has been already proved in solid industry-based CMOS technologies. Dependencies of the physical model parameters on channel dimensions, are thoroughly investigated, and semi?empirical expressions are derived, which precisely characterize such behaviors for an industry-based GFET technology, as well as for others developed in research labs. This work aims at the establishment of the first industry standard GFET compact model that can be integrated in circuit simulation tools and hence, can contribute to the update of GFET technology from the research level to massive industry production.
@article{arxiv.2401.14674,
title = {A Scalable Compact Model for the Static Drain Current of Graphene FETs},
author = {Nikolaos Mavredakis and Anibal Pacheco-Sanchez and Oihana Txoperena and Elias Torres and David Jiménez},
journal= {arXiv preprint arXiv:2401.14674},
year = {2024}
}