This work demonstrates a novel energy-efficient tunnel FET (TFET)-CMOS hybrid foundry platform for ultralow-power AIoT applications. By utilizing the proposed monolithic integration process, the novel complementary n and p-type Si TFET technology with dopant segregated source junction and self-aligned drain underlap design is successfully integrated into a 300mm CMOS baseline process without CMOS performance penalty and any new materials, experimentally demonstrating the large Ion and record high Ion/Ioff ratio of 10^7 among TFETs by industry-manufacturers. The device performance and variability are also co-optimized for high-volume production. Further circuit-level implementations are presented based on the calibrated compact model. The proposed TFET-CMOS hybrid logic and SRAM topologies show significant energy efficiency improvement with comparable operation speed compared with standard CMOS circuits, indicating its great potential for power-constraint AIoT applications.
@article{arxiv.2410.12390,
title = {A Novel Energy-Efficient Salicide-Enhanced Tunnel Device Technology Based on 300mm Foundry Platform Towards AIoT Applications},
author = {Kaifeng Wang and Qianqian Huang and Yongqin Wu and Ye Ren and Renjie Wei and Zhixuan Wang and Libo Yang and Fangxing Zhang and Kexing Geng and Yiqing Li and Mengxuan Yang and Jin Luo and Ying Liu and Kai Zheng and Jin Kang and Le Ye and Lining Zhang and Weihai Bu and Ru Huang},
journal= {arXiv preprint arXiv:2410.12390},
year = {2024}
}