GPUs rely on large register files to unlock thread-level parallelism for high throughput. Unfortunately, large register files are power hungry, making it important to seek for new approaches to improve their utilization. This paper introduces a new register file organization for efficient register-packing of narrow integer and floating-point operands designed to leverage on advances in static analysis. We show that the hardware/software co-designed register file organization yields a performance improvement of up to 79%, and 18.6%, on average, at a modest output-quality degradation.
@article{arxiv.2006.05693,
title = {A GPU Register File using Static Data Compression},
author = {Alexandra Angerd and Erik Sintorn and Per Stenström},
journal= {arXiv preprint arXiv:2006.05693},
year = {2020}
}