English

Voltage Controlled Memristor Threshold Logic Gates

Emerging Technologies 2016-09-19 v1

Abstract

In this paper, we present a resistive switching memristor cell for implementing universal logic gates. The cell has a weighted control input whose resistance is set based on a control signal that generalizes the operational regime from NAND to NOR functionality. We further show how threshold logic in the voltage-controlled resistive cell can be used to implement a XOR logic. Building on the same principle we implement a half adder and a 4-bit CLA (Carry Look-ahead Adder) and show that in comparison with CMOS-only logic, the proposed system shows significant improvements in terms of device area, power dissipation and leakage power.

Keywords

Cite

@article{arxiv.1609.04919,
  title  = {Voltage Controlled Memristor Threshold Logic Gates},
  author = {Akshay Kumar Maan and Alex Pappachen James},
  journal= {arXiv preprint arXiv:1609.04919},
  year   = {2016}
}

Comments

To appear in 2016 IEEEE Asia Pacific Conference on Circuits & Systems (IEEE APCCAS 2016), Jeju, Korea, October 25-28, 2016

R2 v1 2026-06-22T15:51:32.843Z