Testable Array Multipliers for a Better Utilization of C-Testability and Bijectivity
Hardware Architecture
2022-01-31 v1 Logic in Computer Science
Abstract
This paper presents a design for test (DFT)architecture for fast and scalable testing of array multipliers (MULTs). Regardless of the MULT size, our proposed testable architecture, without major changes in the original architecture, requires only five test vectors. Test pattern generation (TPG) is done by combining C-testability, bijectivity and deterministic TPG methods. Experimental results show 100% fault coverage for single stuck-at faults. The proposed method requires minor testability hardware insertion into the multiplier with extra delay and area overhead of less than 0.5% for a 64-bit multiplier.
Keywords
Cite
@article{arxiv.2201.11978,
title = {Testable Array Multipliers for a Better Utilization of C-Testability and Bijectivity},
author = {Fatemeh Sheikh Shoaei and Alireza Nahvy and Zainalabedin Navabi},
journal= {arXiv preprint arXiv:2201.11978},
year = {2022}
}
Comments
6 pages,8 figures