High Level Synthesis (HLS) tools, like the Intel FPGA SDK for OpenCL, improve design productivity and enable efficient design space exploration guided by simple program directives (pragmas), but may sometimes miss important optimizations necessary for high performance. In this paper, we present a study of the tradeoffs in HLS optimizations, and the potential of a modern HLS tool in automatically optimizing an application. We perform the study on a 5-stage camera ISP pipeline using the Intel FPGA SDK for OpenCL and an Arria 10 FPGA Dev Kit. We show that automatic optimizations in the HLS tool are valuable, achieving a up to 2.7X speedup over equivalent CPU execution. With further hand tuning, however, we can achieve up to 36.5X speedup over CPU. We draw several specific lessons about the effectiveness of automatic optimizations guided by simple directives, and the nature of manual rewriting required for high performance.
@article{arxiv.2201.03558,
title = {Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL},
author = {Adel Ejjeh and Vikram Adve and Rob Rutenbar},
journal= {arXiv preprint arXiv:2201.03558},
year = {2022}
}
Comments
Presented in FPGA'20 as a poster. Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. 2020