DNNs and LLMs increasingly rely on hardware accelerators, including in safety-critical domains, while technology scaling and growing model complexity make hardware faults more frequent. Existing system-level mechanisms typically treat the NPU as a monolithic unit, using coarse-grained replication that incurs prohibitive performance and hardware overheads, leaving a gap between reliability requirements and deployable solutions. To bridge this gap, we present Strix, a full-stack NPU reliability framework on an open-source SoC, spanning micro-architecture, ISA, and programming methods. Strix re-partitions the NPU along the system inference pipeline, identifies dominant failure modes, and attaches targeted safeguards, achieving sub-micro-second fault localisation, error detection, and correction with only 1.04× slowdown and minimal hardware overhead.
@article{arxiv.2604.10484,
title = {Strix: Re-thinking NPU Reliability from a System Perspective},
author = {Jiapeng Guan and Jie Zhang and Hao Zhou and Ran Wei and Dean You and Hui Wang and Yingquan Wang and Tinglue Wang and Xudong Zhao and Jing Li and Zhe Jiang},
journal= {arXiv preprint arXiv:2604.10484},
year = {2026}
}
Comments
This paper has been accepted for publication at DAC 2026