Stochastic Testing Simulator for Integrated Circuits and MEMS: Hierarchical and Sparse Techniques
Abstract
Process variations are a major concern in today's chip design since they can significantly degrade chip performance. To predict such degradation, existing circuit and MEMS simulators rely on Monte Carlo algorithms, which are typically too slow. Therefore, novel fast stochastic simulators are highly desired. This paper first reviews our recently developed stochastic testing simulator that can achieve speedup factors of hundreds to thousands over Monte Carlo. Then, we develop a fast hierarchical stochastic spectral simulator to simulate a complex circuit or system consisting of several blocks. We further present a fast simulation approach based on anchored ANOVA (analysis of variance) for some design problems with many process variations. This approach can reduce the simulation cost and can identify which variation sources have strong impacts on the circuit's performance. The simulation results of some circuit and MEMS examples are reported to show the effectiveness of our simulator
Cite
@article{arxiv.1409.4822,
title = {Stochastic Testing Simulator for Integrated Circuits and MEMS: Hierarchical and Sparse Techniques},
author = {Zheng Zhang and Xiu Yang and Giovanni Marucci and Paolo Maffezzoni and Ibrahim and M. Elfadel and George Em Karniadakis and Luca Daniel},
journal= {arXiv preprint arXiv:1409.4822},
year = {2016}
}
Comments
Accepted to IEEE Custom Integrated Circuits Conference in June 2014. arXiv admin note: text overlap with arXiv:1407.3023