Hardware accelerators are essential for achieving low-latency, energy-efficient inference in edge applications like image recognition. Spiking Neural Networks (SNNs) are particularly promising due to their event-driven and temporally sparse nature, making them well-suited for low-power Field Programmable Gate Array (FPGA)-based deployment. This paper explores using the open-source Spiker+ framework to generate optimized SNNs accelerators for handwritten digit recognition on the MNIST dataset. Spiker+ enables high-level specification of network topologies, neuron models, and quantization, automatically generating deployable HDL. We evaluate multiple configurations and analyze trade-offs relevant to edge computing constraints.
@article{arxiv.2507.10561,
title = {SFATTI: Spiking FPGA Accelerator for Temporal Task-driven Inference -- A Case Study on MNIST},
author = {Alessio Caviglia and Filippo Marostica and Alessio Carpegna and Alessandro Savino and Stefano Di Carlo},
journal= {arXiv preprint arXiv:2507.10561},
year = {2026}
}