Developing ultra-low-energy superconducting computing and fault-tolerant quantum computing will require scalable superconducting memory. While conventional superconducting logic-based memory cells have facilitated early demonstrations, their large footprint poses a significant barrier to scaling. Nanowire-based superconducting memory cells offer a compact alternative, but high error rates have hindered their integration into large arrays. In this work, we present a superconducting nanowire memory array designed for scalable row-column operation, achieving a functional density of 2.6Mb/cm2. The array operates at 1.3K, where we implement and characterize multi-flux quanta state storage and destructive readout. By optimizing write and read pulse sequences, we minimize bit errors while maximizing operational margins in a 4×4 array. Circuit-level simulations further elucidate the memory cell's dynamics, providing insight into performance limits and stability under varying pulse amplitudes. We experimentally demonstrate stable memory operation with a minimum bit error rate of 10−5. These results suggest a promising path for scaling superconducting nanowire memories to high-density architectures, offering a foundation for energy-efficient memory in superconducting electronics.
@article{arxiv.2503.22897,
title = {Scalable Superconducting Nanowire Memory Array with Row-Column Addressing},
author = {Owen Medeiros and Matteo Castellani and Valentin Karam and Reed Foster and Alejandro Simon and Francesca Incalza and Brenden Butters and Marco Colangelo and Karl K Berggren},
journal= {arXiv preprint arXiv:2503.22897},
year = {2025}
}