The automatic generation of RTL code (e.g., Verilog) using natural language instructions and large language models (LLMs) has attracted significant research interest recently. However, most existing approaches heavily rely on commercial LLMs such as ChatGPT, while open-source LLMs tailored for this specific design generation task exhibit notably inferior performance. The absence of high-quality open-source solutions restricts the flexibility and data privacy of this emerging technique. In this study, we present a new customized LLM solution with a modest parameter count of only 7B, achieving better performance than GPT-3.5 on all representative benchmarks for RTL code generation. Especially, it outperforms GPT-4 in VerilogEval Machine benchmark. This remarkable balance between accuracy and efficiency is made possible by leveraging our new RTL code dataset and a customized LLM algorithm, both of which have been made fully open-source.
@article{arxiv.2312.08617,
title = {RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution},
author = {Shang Liu and Wenji Fang and Yao Lu and Qijun Zhang and Hongce Zhang and Zhiyao Xie},
journal= {arXiv preprint arXiv:2312.08617},
year = {2025}
}
Comments
This is the LAD Conference version of RTLCoder, for the TCAD extension version, please refer to: arXiv:2312.08617v4